Buffer Testing Report

Buffer Circuit Testing
Nick Brewster
25th March 2009
Version 1

The original circuit diagram (shown in figure 1) was not running as intended in simulations. The capacitor C1 was charging far too slowly (figure 2), and the output was oscillating between 0 and 3 volts (figure 3). Figure 4 shows input voltage. The output should rise to 4V very quickly (in the order of nanoseconds) then remain at that voltage whether there is an input connected or not. Then when the switch J2 is closed, the circuit should be reset to 0V until the switch is reopened.
Unfortunately the amp that we are currently intending to use at U4A in the diagram is not available in the simulation software, so a replacement had to be found that had similar specifications in order to simulate the operation of the circuit. The actual amp is currently the LMH6642. This is the same for the diode D3, the intended diode is the 1N34A, which is unavailable in the software, so a replacement was found for simulation. These will be monitored as a possible source of problems since they are not intended to be used in the final circuit.


Figure 1: original circuit design.


Figure 2: Capacitor voltage.


Figure 3: Output voltage.


Figure 4: Input voltage
Chris Whitford was contacted for assistance in the problem, who suggested that the capacitor value was too large, and resistor R3 was also too large. Further tweaks were suggested that should improve the circuit, such as making amp U5A the same as U4A so that there is a high speed amp for the output that can track the value from the first amp. Also replacing amp U6A, however these would only help the circuit run better, changing the resistor and capacitor values would enable the circuit to run as needed, so initially only these were changed.
Capacitor C1 was changed to 1nF and resistor R3 was changed to 100Ω. The rest of the circuit remained unchanged. Figures 5 and 6 show capacitor and output voltages respectively.


Figure 5: Capacitor voltage of edited circuit.


Figure 6: Output voltage of edited circuit.
Capacitor was discharging far too quickly, and the output voltage was just matching the capacitors voltage. I fiddled around with the values of the capacitor and resistor R3 myself to try to allow slower discharging of the capacitor, but could not find a solution to the problem.
Then sat down with Phil to try to find a solution. Since the capacitor was discharging, it was assumed that the input bias current of the first amp U4A was too large, which was causing the capacitor to discharge too quickly. This was replaced with the same amp as U5A, the LMC6462 which has a lower input bias current. The input voltage was also changed to oscillate between 0 and 4 V. Figures 7 and 8 show the capacitor and output voltages respectively.


Figure 7: Capacitor voltage of 3rd design of circuit. The dip just after 70ms is where switch J2 was closed to activate the FET and reset the circuit. The switch was then reopened and the circuit resumed function.


Figure 8: Output voltage of 3rd stage of circuit. The dip in voltage is again where the circuit was reset via the FET.

This shows the circuit is running as it should, however using a much slower amp at U4A than the one than we will actually be using. The rise time of the voltage is much slower than needed. As in figure 9, the rise time can be seen to be around 1.5ms (a square waveform was used to obtain this), where it actually needs to be on the scale of nanoseconds. In order to do this a faster amp needs to be used, however using a faster amp means the input bias current is much too big, so discharges the capacitor too quickly. An amp must be found that has a fast slew rate (>200V/µs) and a very low input bias current (approx <100nA). If this cannot be found, or indeed does not exist, an alternative solution must be found.


Figure 9: Rise time of capacitor voltage approx 1.5ms.

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